In part one of this article we examined ground-breaking techniques used by Intel in its 45-nm, high-k, metal-gate (HKMG) Penryn series of chips. Here we start by examining how well the actual product compared with the sacrificial polysilicon pattern shown in Fig. 5.
The SEM images cannot give us enough detail because, as a surface imaging technique, it cannot distinguish the spacers from the metal in the gates. Figure 6 is a plan-view TEM image of a pair of combined PMOS/NMOS gates from the SRAM, and they have kept the square profile fairly well through the etch, metal deposition, and CMP steps required to make the metal gate structure. The PMOS transistors are distinguished by the mottled texture of the titanium nitride used in the PMOS gates, as opposed the aluminium fill used in the NMOS. The sidewall spacers can be seen as a faint ghosting around the gate electrodes.
However, if we look outside the SRAM array (Fig. 7), more rounded outlines are found, so it appears that the array transistors are particularly tuned to be square-ended; which is not unreasonable, since nearly half the chip is taken up by the SRAM cache memory.
When it comes to the metal levels, at M1 it seems that dual-APSM has been used (double masking as opposed to double patterning). Fig. 3 shows the “wiggle” in the VDD line, and Figure 8 shows an area of standard cells in the logic array, with some very tight Manhattan layout in the cells. It was in these areas that we found the tightest M1 pitch, closer to 150 nm than the announced 160 nm .
With features this densely spaced, and using dry exposure tools, it is obviously a daunting task to define patterns without any faults, even with APSM and the most advanced reticle enhancement and optical proximity correction techniques. Dual APSM takes the hypothesis that phase conflicts can be avoided for both masks, if apertures oriented along the vertical direction are assigned to one mask, and those along the horizontal direction to the other . If Intel is using dual-APSM, I think the hypothesis is proven!
At M2, we found a very limited use of orthogonal patterning, and M3 none at all; but since the pitch is still 160 nm, it is possible that dual masking was used, although the M3 masks would be oriented in the same direction.
If we look again at Fig.8, we can see that some of the lines between the logic cells are a darker shade of grey than others in the cells. This is a function of the secondary electrons seen by the SEM detector, but for our purposes it indicates dummy metal lines used in the layout of the part. The same effect is shown (Fig. 9) at M2 and M3. In other parts of the die Intel has used dummy metal for a much greater proportion of the area, particularly at the M1 level (Fig. 10).
Of course, the use of dummy metal is almost as old as the use of CMP, but this is the first time we have seen it employed so extensively, so densely, and so early in the back-end processing. For CMP control we usually see small structures such as squares of metal – here the dummy structures are lines squeezed in at every possible position where there is no active metal needed. However, the regularity of this layout cannot but reduce the lithographic variation, and coupled with CMP improvements (Fig. 11), we get the impressive metallization seen in Figs 1-3.
We also found the same layout philosophy used at the gate level. Figure 12 is an example of an area of general logic (note that the diffusions are covered by dielectric material in this image). Repetitive columns of metal gate fingers are arranged parallel to columns of M0 trench contacts. In regions where no active devices are required, these metal gate strips serve as dummy structures. Where an active device is required, the column is simply broken, long enough to form a gate finger, and continues on again beyond the device as dummy metal. In the same way, the W trench contacts can be tailored to any length necessary.
This layout has several advantages; in addition to aiding lithography, the use of trench contacts also enables flexibility in choosing where to place a contact up to metal 1. The trenches can be routed to a region over STI to form a contact land, as opposed to being forced to contact the top of a conventional contact stud over active Si. The trench contacts also form butted, or split, contacts enabling connection of one or several gates to one or several diffusions, without the use of a metal 1 strap. Numerous manufacturers have used butted contacts as a means to reduce the unit 6T SRAM cell size, but the Penryn die marks the first time we have seen Intel use butted contacts to increase packing density in the core logic blocks.
Intel had mentioned this “dummification” technique in a presentation at their 2006 Developer Forum , and in addition to the above advantages, they claim that it reduces leakage (Fig. 13) and improves thermal processing (Fig. 14).
To monitor the end-of-line results, Intel designers place ring oscillators in all product designs. Performance data such as fmax can be used to identify areas of concern, and give a measure of the systematic and random variation seen in the process. Figure 15 shows the trend in fmax over recent process generations, and the 45-nm data is slightly improved over the 65-nm process.
I had the opportunity of chatting with Kelin Kuhn at IEDM, and she commented that despite all the work that they had done on improving individual process steps, and using the kind of design and layout changes we have seen above to reduce variations in the final product, they were actually pleasantly surprised to see the first chips come out of the fab with variation so well controlled. Judging by the limited sample seen in our analyses, their efforts have paid off admirably!
 K. Mistry et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging”, Proc IEDM, 2007 pp. 247 – 250; http://download.intel.com/technology/IEDM2007/HiKMG_paper.pdf; http://download.intel.com/technology/iedm2007/HiKMG_pres.pdf
 D. James “An Ongoing History of Strain – Now Available with High-k!” WeSRCH paper http://electronics.wesrch.com/Paper/paper_details.php?id=EL1SE1YJ9AKVU&paper_type=pdf&type=%20latest
 K. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”, Proc. IEDM, 2007, pp. 471 – 474; http://download.intel.com/technology/IEDM2007/variation.pdf, http://download.intel.com/technology/IEDM2007/variation_pres.pdf
 D. Bernard et al., “Clear-field dual alternating phase-shift mask lithography” Optical Microlithography XV, Proc. SPIE Vol. 4691, p. 999-1008.
 S. Rikhi et al., “Design for manufacturing”, IDF 2006, session EPRS008